// (C) 2022 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other 
// software and tools, and its AMPP partner logic functions, and any output 
// files from any of the foregoing (including device programming or simulation 
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// to the terms and conditions of the Intel Program License Subscription 
// Agreement, Intel FPGA IP License Agreement, or other applicable 
// license agreement, including, without limitation, that your use is for the 
// sole purpose of programming logic devices manufactured by Intel and sold by 
// Intel or its authorized distributors.  Please refer to the applicable 
// agreement for further details.

`timescale 1 ps / 1 ps
module adc_modular_dual_adc_0 (
		input  wire        clock_clk,                  //            clock.clk
		input  wire        reset_sink_reset_n,         //       reset_sink.reset_n
		input  wire        adc_pll_clock_clk,          //    adc_pll_clock.clk
		input  wire        adc_pll_locked_export,      //   adc_pll_locked.export
		input  wire        sequencer_csr_address,      //    sequencer_csr.address
		input  wire        sequencer_csr_read,         //                 .read
		input  wire        sequencer_csr_write,        //                 .write
		input  wire [31:0] sequencer_csr_writedata,    //                 .writedata
		output wire [31:0] sequencer_csr_readdata,     //                 .readdata
		input  wire [6:0]  sample_store_csr_address,   // sample_store_csr.address
		input  wire        sample_store_csr_read,      //                 .read
		input  wire        sample_store_csr_write,     //                 .write
		input  wire [31:0] sample_store_csr_writedata, //                 .writedata
		output wire [31:0] sample_store_csr_readdata,  //                 .readdata
		output wire        sample_store_irq_irq        // sample_store_irq.irq
	);

	wire         conduit_splitter_internal_conduit_out_1_internal_conduit_in; // conduit_splitter_internal:clk_in_pll_locked_out_1 -> control_internal:clk_in_pll_locked
	wire         conduit_splitter_internal_conduit_out_2_internal_conduit_in; // conduit_splitter_internal:clk_in_pll_locked_out_2 -> control_internal_2:clk_in_pll_locked
	wire         sequencer_internal_command_valid;                            // sequencer_internal:cmd_valid -> control_internal:cmd_valid
	wire         sequencer_internal_command_ready;                            // control_internal:cmd_ready -> sequencer_internal:cmd_ready
	wire   [4:0] sequencer_internal_command_channel;                          // sequencer_internal:cmd_channel -> control_internal:cmd_channel
	wire         sequencer_internal_command_startofpacket;                    // sequencer_internal:cmd_sop -> control_internal:cmd_sop
	wire         sequencer_internal_command_endofpacket;                      // sequencer_internal:cmd_eop -> control_internal:cmd_eop
	wire         sequencer_internal_command_2_valid;                          // sequencer_internal:cmd_valid_2 -> control_internal_2:cmd_valid
	wire         sequencer_internal_command_2_ready;                          // control_internal_2:cmd_ready -> sequencer_internal:cmd_ready_2
	wire   [4:0] sequencer_internal_command_2_channel;                        // sequencer_internal:cmd_channel_2 -> control_internal_2:cmd_channel
	wire         sequencer_internal_command_2_startofpacket;                  // sequencer_internal:cmd_sop_2 -> control_internal_2:cmd_sop
	wire         sequencer_internal_command_2_endofpacket;                    // sequencer_internal:cmd_eop_2 -> control_internal_2:cmd_eop
	wire         control_internal_sync_handshake_valid;                       // control_internal:sync_valid -> dual_sync_internal:sync_1_valid
	wire         control_internal_sync_handshake_ready;                       // dual_sync_internal:sync_1_ready -> control_internal:sync_ready
	wire         control_internal_2_sync_handshake_valid;                     // control_internal_2:sync_valid -> dual_sync_internal:sync_2_valid
	wire         control_internal_2_sync_handshake_ready;                     // dual_sync_internal:sync_2_ready -> control_internal_2:sync_ready
	wire         response_merge_internal_response_out_valid;                  // response_merge_internal:rsp_out_valid -> sample_store_internal:rsp_valid
	wire  [23:0] response_merge_internal_response_out_data;                   // response_merge_internal:rsp_out_data -> sample_store_internal:rsp_data
	wire   [4:0] response_merge_internal_response_out_channel;                // response_merge_internal:rsp_out_channel -> sample_store_internal:rsp_channel
	wire         response_merge_internal_response_out_startofpacket;          // response_merge_internal:rsp_out_sop -> sample_store_internal:rsp_sop
	wire         response_merge_internal_response_out_endofpacket;            // response_merge_internal:rsp_out_eop -> sample_store_internal:rsp_eop
	wire         control_internal_response_valid;                             // control_internal:rsp_valid -> response_merge_internal:rsp_in_1_valid
	wire  [11:0] control_internal_response_data;                              // control_internal:rsp_data -> response_merge_internal:rsp_in_1_data
	wire   [4:0] control_internal_response_channel;                           // control_internal:rsp_channel -> response_merge_internal:rsp_in_1_channel
	wire         control_internal_response_startofpacket;                     // control_internal:rsp_sop -> response_merge_internal:rsp_in_1_sop
	wire         control_internal_response_endofpacket;                       // control_internal:rsp_eop -> response_merge_internal:rsp_in_1_eop
	wire         control_internal_2_response_valid;                           // control_internal_2:rsp_valid -> response_merge_internal:rsp_in_2_valid
	wire  [11:0] control_internal_2_response_data;                            // control_internal_2:rsp_data -> response_merge_internal:rsp_in_2_data
	wire   [4:0] control_internal_2_response_channel;                         // control_internal_2:rsp_channel -> response_merge_internal:rsp_in_2_channel
	wire         control_internal_2_response_startofpacket;                   // control_internal_2:rsp_sop -> response_merge_internal:rsp_in_2_sop
	wire         control_internal_2_response_endofpacket;                     // control_internal_2:rsp_eop -> response_merge_internal:rsp_in_2_eop

	altera_modular_adc_control #(
		.clkdiv                          (2),
		.tsclkdiv                        (0),
		.tsclksel                        (1),
		.hard_pwd                        (0),
		.prescalar                       (0),
		.refsel                          (1),
		.device_partname_fivechar_prefix ("10M25"),
		.is_this_first_or_second_adc     (1),
		.analog_input_pin_mask           (65791),
		.dual_adc_mode                   (1),
		.enable_usr_sim                  (0),
		.reference_voltage_sim           (49648),
		.simfilename_ch0                 (""),
		.simfilename_ch1                 (""),
		.simfilename_ch2                 (""),
		.simfilename_ch3                 (""),
		.simfilename_ch4                 (""),
		.simfilename_ch5                 (""),
		.simfilename_ch6                 (""),
		.simfilename_ch7                 (""),
		.simfilename_ch8                 (""),
		.simfilename_ch9                 (""),
		.simfilename_ch10                (""),
		.simfilename_ch11                (""),
		.simfilename_ch12                (""),
		.simfilename_ch13                (""),
		.simfilename_ch14                (""),
		.simfilename_ch15                (""),
		.simfilename_ch16                ("")
	) control_internal (
		.clk               (clock_clk),                                                   //          clock.clk
		.cmd_valid         (sequencer_internal_command_valid),                            //        command.valid
		.cmd_channel       (sequencer_internal_command_channel),                          //               .channel
		.cmd_sop           (sequencer_internal_command_startofpacket),                    //               .startofpacket
		.cmd_eop           (sequencer_internal_command_endofpacket),                      //               .endofpacket
		.cmd_ready         (sequencer_internal_command_ready),                            //               .ready
		.sync_valid        (control_internal_sync_handshake_valid),                       // sync_handshake.valid
		.sync_ready        (control_internal_sync_handshake_ready),                       //               .ready
		.rst_n             (reset_sink_reset_n),                                          //     reset_sink.reset_n
		.rsp_valid         (control_internal_response_valid),                             //       response.valid
		.rsp_channel       (control_internal_response_channel),                           //               .channel
		.rsp_data          (control_internal_response_data),                              //               .data
		.rsp_sop           (control_internal_response_startofpacket),                     //               .startofpacket
		.rsp_eop           (control_internal_response_endofpacket),                       //               .endofpacket
		.clk_in_pll_c0     (adc_pll_clock_clk),                                           //  adc_pll_clock.clk
		.clk_in_pll_locked (conduit_splitter_internal_conduit_out_1_internal_conduit_in)  //    conduit_end.internal_conduit_in
	);

	altera_modular_adc_control #(
		.clkdiv                          (2),
		.tsclkdiv                        (0),
		.tsclksel                        (1),
		.hard_pwd                        (0),
		.prescalar                       (0),
		.refsel                          (1),
		.device_partname_fivechar_prefix ("10M25"),
		.is_this_first_or_second_adc     (2),
		.analog_input_pin_mask           (65791),
		.dual_adc_mode                   (1),
		.enable_usr_sim                  (0),
		.reference_voltage_sim           (49648),
		.simfilename_ch0                 (""),
		.simfilename_ch1                 (""),
		.simfilename_ch2                 (""),
		.simfilename_ch3                 (""),
		.simfilename_ch4                 (""),
		.simfilename_ch5                 (""),
		.simfilename_ch6                 (""),
		.simfilename_ch7                 (""),
		.simfilename_ch8                 (""),
		.simfilename_ch9                 (""),
		.simfilename_ch10                (""),
		.simfilename_ch11                (""),
		.simfilename_ch12                (""),
		.simfilename_ch13                (""),
		.simfilename_ch14                (""),
		.simfilename_ch15                (""),
		.simfilename_ch16                ("")
	) control_internal_2 (
		.clk               (clock_clk),                                                   //          clock.clk
		.cmd_valid         (sequencer_internal_command_2_valid),                          //        command.valid
		.cmd_channel       (sequencer_internal_command_2_channel),                        //               .channel
		.cmd_sop           (sequencer_internal_command_2_startofpacket),                  //               .startofpacket
		.cmd_eop           (sequencer_internal_command_2_endofpacket),                    //               .endofpacket
		.cmd_ready         (sequencer_internal_command_2_ready),                          //               .ready
		.sync_valid        (control_internal_2_sync_handshake_valid),                     // sync_handshake.valid
		.sync_ready        (control_internal_2_sync_handshake_ready),                     //               .ready
		.rst_n             (reset_sink_reset_n),                                          //     reset_sink.reset_n
		.rsp_valid         (control_internal_2_response_valid),                           //       response.valid
		.rsp_channel       (control_internal_2_response_channel),                         //               .channel
		.rsp_data          (control_internal_2_response_data),                            //               .data
		.rsp_sop           (control_internal_2_response_startofpacket),                   //               .startofpacket
		.rsp_eop           (control_internal_2_response_endofpacket),                     //               .endofpacket
		.clk_in_pll_c0     (adc_pll_clock_clk),                                           //  adc_pll_clock.clk
		.clk_in_pll_locked (conduit_splitter_internal_conduit_out_2_internal_conduit_in)  //    conduit_end.internal_conduit_in
	);

	altera_modular_adc_sequencer #(
		.DUAL_ADC_MODE    (1),
		.CSD_LENGTH       (9),
		.CSD_SLOT_0       (5'b00000),
		.CSD_SLOT_1       (5'b00001),
		.CSD_SLOT_2       (5'b00010),
		.CSD_SLOT_3       (5'b00011),
		.CSD_SLOT_4       (5'b00100),
		.CSD_SLOT_5       (5'b00101),
		.CSD_SLOT_6       (5'b00110),
		.CSD_SLOT_7       (5'b00111),
		.CSD_SLOT_8       (5'b01000),
		.CSD_SLOT_9       (5'b00000),
		.CSD_SLOT_10      (5'b00000),
		.CSD_SLOT_11      (5'b00000),
		.CSD_SLOT_12      (5'b00000),
		.CSD_SLOT_13      (5'b00000),
		.CSD_SLOT_14      (5'b00000),
		.CSD_SLOT_15      (5'b00000),
		.CSD_SLOT_16      (5'b00000),
		.CSD_SLOT_17      (5'b00000),
		.CSD_SLOT_18      (5'b00000),
		.CSD_SLOT_19      (5'b00000),
		.CSD_SLOT_20      (5'b00000),
		.CSD_SLOT_21      (5'b00000),
		.CSD_SLOT_22      (5'b00000),
		.CSD_SLOT_23      (5'b00000),
		.CSD_SLOT_24      (5'b00000),
		.CSD_SLOT_25      (5'b00000),
		.CSD_SLOT_26      (5'b00000),
		.CSD_SLOT_27      (5'b00000),
		.CSD_SLOT_28      (5'b00000),
		.CSD_SLOT_29      (5'b00000),
		.CSD_SLOT_30      (5'b00000),
		.CSD_SLOT_31      (5'b00000),
		.CSD_SLOT_32      (5'b00000),
		.CSD_SLOT_33      (5'b00000),
		.CSD_SLOT_34      (5'b00000),
		.CSD_SLOT_35      (5'b00000),
		.CSD_SLOT_36      (5'b00000),
		.CSD_SLOT_37      (5'b00000),
		.CSD_SLOT_38      (5'b00000),
		.CSD_SLOT_39      (5'b00000),
		.CSD_SLOT_40      (5'b00000),
		.CSD_SLOT_41      (5'b00000),
		.CSD_SLOT_42      (5'b00000),
		.CSD_SLOT_43      (5'b00000),
		.CSD_SLOT_44      (5'b00000),
		.CSD_SLOT_45      (5'b00000),
		.CSD_SLOT_46      (5'b00000),
		.CSD_SLOT_47      (5'b00000),
		.CSD_SLOT_48      (5'b00000),
		.CSD_SLOT_49      (5'b00000),
		.CSD_SLOT_50      (5'b00000),
		.CSD_SLOT_51      (5'b00000),
		.CSD_SLOT_52      (5'b00000),
		.CSD_SLOT_53      (5'b00000),
		.CSD_SLOT_54      (5'b00000),
		.CSD_SLOT_55      (5'b00000),
		.CSD_SLOT_56      (5'b00000),
		.CSD_SLOT_57      (5'b00000),
		.CSD_SLOT_58      (5'b00000),
		.CSD_SLOT_59      (5'b00000),
		.CSD_SLOT_60      (5'b00000),
		.CSD_SLOT_61      (5'b00000),
		.CSD_SLOT_62      (5'b00000),
		.CSD_SLOT_63      (5'b00000),
		.CSD_SLOT_0_ADC2  (5'b00000),
		.CSD_SLOT_1_ADC2  (5'b00001),
		.CSD_SLOT_2_ADC2  (5'b00010),
		.CSD_SLOT_3_ADC2  (5'b00011),
		.CSD_SLOT_4_ADC2  (5'b00100),
		.CSD_SLOT_5_ADC2  (5'b00101),
		.CSD_SLOT_6_ADC2  (5'b00110),
		.CSD_SLOT_7_ADC2  (5'b00111),
		.CSD_SLOT_8_ADC2  (5'b01000),
		.CSD_SLOT_9_ADC2  (5'b00000),
		.CSD_SLOT_10_ADC2 (5'b00000),
		.CSD_SLOT_11_ADC2 (5'b00000),
		.CSD_SLOT_12_ADC2 (5'b00000),
		.CSD_SLOT_13_ADC2 (5'b00000),
		.CSD_SLOT_14_ADC2 (5'b00000),
		.CSD_SLOT_15_ADC2 (5'b00000),
		.CSD_SLOT_16_ADC2 (5'b00000),
		.CSD_SLOT_17_ADC2 (5'b00000),
		.CSD_SLOT_18_ADC2 (5'b00000),
		.CSD_SLOT_19_ADC2 (5'b00000),
		.CSD_SLOT_20_ADC2 (5'b00000),
		.CSD_SLOT_21_ADC2 (5'b00000),
		.CSD_SLOT_22_ADC2 (5'b00000),
		.CSD_SLOT_23_ADC2 (5'b00000),
		.CSD_SLOT_24_ADC2 (5'b00000),
		.CSD_SLOT_25_ADC2 (5'b00000),
		.CSD_SLOT_26_ADC2 (5'b00000),
		.CSD_SLOT_27_ADC2 (5'b00000),
		.CSD_SLOT_28_ADC2 (5'b00000),
		.CSD_SLOT_29_ADC2 (5'b00000),
		.CSD_SLOT_30_ADC2 (5'b00000),
		.CSD_SLOT_31_ADC2 (5'b00000),
		.CSD_SLOT_32_ADC2 (5'b00000),
		.CSD_SLOT_33_ADC2 (5'b00000),
		.CSD_SLOT_34_ADC2 (5'b00000),
		.CSD_SLOT_35_ADC2 (5'b00000),
		.CSD_SLOT_36_ADC2 (5'b00000),
		.CSD_SLOT_37_ADC2 (5'b00000),
		.CSD_SLOT_38_ADC2 (5'b00000),
		.CSD_SLOT_39_ADC2 (5'b00000),
		.CSD_SLOT_40_ADC2 (5'b00000),
		.CSD_SLOT_41_ADC2 (5'b00000),
		.CSD_SLOT_42_ADC2 (5'b00000),
		.CSD_SLOT_43_ADC2 (5'b00000),
		.CSD_SLOT_44_ADC2 (5'b00000),
		.CSD_SLOT_45_ADC2 (5'b00000),
		.CSD_SLOT_46_ADC2 (5'b00000),
		.CSD_SLOT_47_ADC2 (5'b00000),
		.CSD_SLOT_48_ADC2 (5'b00000),
		.CSD_SLOT_49_ADC2 (5'b00000),
		.CSD_SLOT_50_ADC2 (5'b00000),
		.CSD_SLOT_51_ADC2 (5'b00000),
		.CSD_SLOT_52_ADC2 (5'b00000),
		.CSD_SLOT_53_ADC2 (5'b00000),
		.CSD_SLOT_54_ADC2 (5'b00000),
		.CSD_SLOT_55_ADC2 (5'b00000),
		.CSD_SLOT_56_ADC2 (5'b00000),
		.CSD_SLOT_57_ADC2 (5'b00000),
		.CSD_SLOT_58_ADC2 (5'b00000),
		.CSD_SLOT_59_ADC2 (5'b00000),
		.CSD_SLOT_60_ADC2 (5'b00000),
		.CSD_SLOT_61_ADC2 (5'b00000),
		.CSD_SLOT_62_ADC2 (5'b00000),
		.CSD_SLOT_63_ADC2 (5'b00000)
	) sequencer_internal (
		.clk           (clock_clk),                                  //      clock.clk
		.rst_n         (reset_sink_reset_n),                         // reset_sink.reset_n
		.cmd_ready     (sequencer_internal_command_ready),           //    command.ready
		.cmd_valid     (sequencer_internal_command_valid),           //           .valid
		.cmd_channel   (sequencer_internal_command_channel),         //           .channel
		.cmd_sop       (sequencer_internal_command_startofpacket),   //           .startofpacket
		.cmd_eop       (sequencer_internal_command_endofpacket),     //           .endofpacket
		.cmd_ready_2   (sequencer_internal_command_2_ready),         //  command_2.ready
		.cmd_valid_2   (sequencer_internal_command_2_valid),         //           .valid
		.cmd_channel_2 (sequencer_internal_command_2_channel),       //           .channel
		.cmd_sop_2     (sequencer_internal_command_2_startofpacket), //           .startofpacket
		.cmd_eop_2     (sequencer_internal_command_2_endofpacket),   //           .endofpacket
		.addr          (sequencer_csr_address),                      //        csr.address
		.read          (sequencer_csr_read),                         //           .read
		.write         (sequencer_csr_write),                        //           .write
		.writedata     (sequencer_csr_writedata),                    //           .writedata
		.readdata      (sequencer_csr_readdata)                      //           .readdata
	);

	altera_modular_adc_sample_store #(
		.DUAL_ADC_MODE  (1),
		.RSP_DATA_WIDTH (24)
	) sample_store_internal (
		.clk         (clock_clk),                                          //            clock.clk
		.rst_n       (reset_sink_reset_n),                                 //       reset_sink.reset_n
		.rsp_valid   (response_merge_internal_response_out_valid),         //         response.valid
		.rsp_channel (response_merge_internal_response_out_channel),       //                 .channel
		.rsp_sop     (response_merge_internal_response_out_startofpacket), //                 .startofpacket
		.rsp_eop     (response_merge_internal_response_out_endofpacket),   //                 .endofpacket
		.rsp_data    (response_merge_internal_response_out_data),          //                 .data
		.addr        (sample_store_csr_address),                           //              csr.address
		.read        (sample_store_csr_read),                              //                 .read
		.write       (sample_store_csr_write),                             //                 .write
		.writedata   (sample_store_csr_writedata),                         //                 .writedata
		.readdata    (sample_store_csr_readdata),                          //                 .readdata
		.irq         (sample_store_irq_irq)                                // interrupt_sender.irq
	);

	altera_modular_adc_conduit_splitter conduit_splitter_internal (
		.clk                     (clock_clk),                                                   //         clock.clk
		.rst_n                   (reset_sink_reset_n),                                          //    reset_sink.reset_n
		.clk_in_pll_locked       (adc_pll_locked_export),                                       //    conduit_in.export
		.clk_in_pll_locked_out_1 (conduit_splitter_internal_conduit_out_1_internal_conduit_in), // conduit_out_1.internal_conduit_in
		.clk_in_pll_locked_out_2 (conduit_splitter_internal_conduit_out_2_internal_conduit_in)  // conduit_out_2.internal_conduit_in
	);

	altera_modular_adc_dual_sync dual_sync_internal (
		.clk          (clock_clk),                               //            clock.clk
		.rst_n        (reset_sink_reset_n),                      //       reset_sink.reset_n
		.sync_1_valid (control_internal_sync_handshake_valid),   // sync_handshake_1.valid
		.sync_1_ready (control_internal_sync_handshake_ready),   //                 .ready
		.sync_2_valid (control_internal_2_sync_handshake_valid), // sync_handshake_2.valid
		.sync_2_ready (control_internal_2_sync_handshake_ready)  //                 .ready
	);

	altera_modular_adc_response_merge response_merge_internal (
		.clk              (clock_clk),                                          //         clock.clk
		.rst_n            (reset_sink_reset_n),                                 //    reset_sink.reset_n
		.rsp_in_1_valid   (control_internal_response_valid),                    // response_in_1.valid
		.rsp_in_1_channel (control_internal_response_channel),                  //              .channel
		.rsp_in_1_data    (control_internal_response_data),                     //              .data
		.rsp_in_1_sop     (control_internal_response_startofpacket),            //              .startofpacket
		.rsp_in_1_eop     (control_internal_response_endofpacket),              //              .endofpacket
		.rsp_in_2_valid   (control_internal_2_response_valid),                  // response_in_2.valid
		.rsp_in_2_channel (control_internal_2_response_channel),                //              .channel
		.rsp_in_2_data    (control_internal_2_response_data),                   //              .data
		.rsp_in_2_sop     (control_internal_2_response_startofpacket),          //              .startofpacket
		.rsp_in_2_eop     (control_internal_2_response_endofpacket),            //              .endofpacket
		.rsp_out_valid    (response_merge_internal_response_out_valid),         //  response_out.valid
		.rsp_out_channel  (response_merge_internal_response_out_channel),       //              .channel
		.rsp_out_data     (response_merge_internal_response_out_data),          //              .data
		.rsp_out_sop      (response_merge_internal_response_out_startofpacket), //              .startofpacket
		.rsp_out_eop      (response_merge_internal_response_out_endofpacket)    //              .endofpacket
	);

endmodule
